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XCVU13P-L2FLGA2577E
IC FPGA 448 I/O 2577FCBGA
- メーカー
- Mfr。パート #XCVU13P-L2FLGA2577E
- パッケージ 2577-BBGA, FCBGA
- データシート
- 在庫中8385
100% オリジナル &新しい
出荷の準備ができている24時間
365日の保証
RFQおよびもっと割引を得る
仕様
| Supplier | AMD Xilinx |
| Package | Tray |
| Series | Virtex® UltraScale+™ |
| ProductStatus | Active |
| NumberofLABs/CLBs | 216000 |
| NumberofLogicElements/Cells | 3780000 |
| TotalRAMBits | 514867200 |
| NumberofI/O | 448 |
| Voltage-Supply | 0.698V ~ 0.876V |
| MountingType | Surface Mount |
| OperatingTemperature | 0°C ~ 110°C (TJ) |
| Package/Case | 2577-BBGA, FCBGA |
概要
Description
XCVU13P-L2FLGA2577E is a Virtex UltraScale+ FPGA from Xilinx (now AMD) in a flip-chip land-grid-array package. The “L2” is speed grade -2; “FLGA” indicates flip-chip LGA packaging; “2577” refers to 2,577 I/O balls; “E” typically denotes industrial temperature range.
Key points:
- High-density FPGA fabric for demanding workloads (data center, telecom, 5G, AI/ML acceleration, network offload).
- Rich mix of resources: large programmable logic (logic cells/LUTs), DSP slices, Block RAM and UltraRAM, plus many high-speed serial transceivers for multi-gigabit I/O.
- Supports advanced features and connectivity (PCIe cores, memory interfaces, partial dynamic reconfiguration) via the Xilinx Vivado/Vitis toolchain.
Use cases:
- Packet processing, programmable acceleration, software-defined radio, high-bandwidth protocol offload.
Note:
- For exact resource counts (logic cells, LUTs, DSP48s, BRAM/URAM, transceiver count/speed), refer to the official datasheet and packaging summary.
Key points:
- High-density FPGA fabric for demanding workloads (data center, telecom, 5G, AI/ML acceleration, network offload).
- Rich mix of resources: large programmable logic (logic cells/LUTs), DSP slices, Block RAM and UltraRAM, plus many high-speed serial transceivers for multi-gigabit I/O.
- Supports advanced features and connectivity (PCIe cores, memory interfaces, partial dynamic reconfiguration) via the Xilinx Vivado/Vitis toolchain.
Use cases:
- Packet processing, programmable acceleration, software-defined radio, high-bandwidth protocol offload.
Note:
- For exact resource counts (logic cells, LUTs, DSP48s, BRAM/URAM, transceiver count/speed), refer to the official datasheet and packaging summary.
Features
Key features of XCVU13P-L2FLGA2577E (Versal Premium ACAP):
- Versal ACAP architecture: heterogeneous compute with FPGA fabric, scalar engines, vector engines, and AI Engines (AIE) for ML workloads.
- Large programmable logic with DSP blocks for high-density digital signal processing.
- High-density high-speed transceivers (multi-Gbps SerDes) for versatile I/O and protocol mix.
- Integrated acceleration: AI Engines optimized for neural/ML workloads and data processing.
- Rich connectivity: PCIe and other high-bandwidth interfaces; extensive memory/controller support.
- Security: hardware security features including cryptographic and secure boot capabilities.
- Partial/reconfigurable hardware: dynamic partial reconfiguration for runtime adaptability.
- Power and performance: optimized power-performance with architecture geared for acceleration workloads.
- Package: FLGA2577E (LGA, 2577-ball) for dense I/O and high-speed interconnect.
Note: for exact transceiver counts, memory options, and supported protocols, please refer to the official Xilinx product brief.
- Versal ACAP architecture: heterogeneous compute with FPGA fabric, scalar engines, vector engines, and AI Engines (AIE) for ML workloads.
- Large programmable logic with DSP blocks for high-density digital signal processing.
- High-density high-speed transceivers (multi-Gbps SerDes) for versatile I/O and protocol mix.
- Integrated acceleration: AI Engines optimized for neural/ML workloads and data processing.
- Rich connectivity: PCIe and other high-bandwidth interfaces; extensive memory/controller support.
- Security: hardware security features including cryptographic and secure boot capabilities.
- Partial/reconfigurable hardware: dynamic partial reconfiguration for runtime adaptability.
- Power and performance: optimized power-performance with architecture geared for acceleration workloads.
- Package: FLGA2577E (LGA, 2577-ball) for dense I/O and high-speed interconnect.
Note: for exact transceiver counts, memory options, and supported protocols, please refer to the official Xilinx product brief.
Package
FLGA2577E indicates a Flip-Chip Land Grid Array (FLGA) package with 2,577 balls, i.e., an LGA 2,577-ball package (extended-temperature).
Pinout
- Pin count: 2,577 pins (LGA2577 package)
- Function: XCVU13P is a Versal Premium ACAP FPGA packaged in an L2FLGA2577E; used for high-performance compute/acceleration with programmable logic, DSP, and high-speed transceivers.
- Function: XCVU13P is a Versal Premium ACAP FPGA packaged in an L2FLGA2577E; used for high-performance compute/acceleration with programmable logic, DSP, and high-speed transceivers.
Manufacturer
Manufacturer: Xilinx (now AMD). Xilinx is a U.S.-based semiconductor company that designs FPGAs, adaptive compute acceleration platforms (ACAPs), and SoCs. It was acquired by AMD in 2022 and operates as an AMD subsidiary/brand.
Application
- AI/ML inference and acceleration (edge and data center)
- 5G/telecom networking and network processing
- Vision, image/video processing and sensor fusion
- High-performance computing and data-center acceleration
- Automotive, industrial, aerospace/defense DSP and mission-critical applications
- 5G/telecom networking and network processing
- Vision, image/video processing and sensor fusion
- High-performance computing and data-center acceleration
- Automotive, industrial, aerospace/defense DSP and mission-critical applications
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出荷料参照(DHL/FedEx):
DHL の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は2〜5営業日です。
フェデックス: 配送費は25ドル〜40ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
UPS の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
TNT社: 配送費は25ドル〜65ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
EMS: 配送料金は30〜50ドル(0.5kg)の範囲で、推定配送時間は7〜15営業日です。
登録航空郵便: 配送費は2〜4ドル(0.1kg)で、推定配送時間は5〜20営業日です。
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