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XC2S200E-6PQG208C
IC FPGA 146 I/O 208QFP
- メーカー
- Mfr。パート #XC2S200E-6PQG208C
- パッケージ PQFP-208
- データシート
- 在庫中2890
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仕様
| Package | Tray |
| Series | Spartan®-IIE |
| ProductStatus | Obsolete |
| NumberofLABs/CLBs | 1176 |
| NumberofLogicElements/Cells | 5292 |
| TotalRAMBits | 57344 |
| NumberofI/O | 146 |
| NumberofGates | 200000 |
| Voltage-Supply | 1.71V ~ 1.89V |
| MountingType | Surface Mount |
| OperatingTemperature | 0°C ~ 85°C (TJ) |
| Package/Case | 208-BFQFP |
概要
Description
XC2S200E-6PQG208C is a Xilinx Spartan-2E FPGA. It’s a low-cost, SRAM-based reprogrammable logic device designed for moderate-density digital logic.
Key points:
- Density: about 200K system gates (roughly tens of thousands of logic elements).
- Package: 208-pin Plastic Quad Flat Gate (PQG208).
- Speed: -6 speed grade (faster timing options unavailable in this line).
- Architecture: configurable logic blocks (LUTs/FFs), distributed RAM, flexible I/O blocks across banks, suitable for glue logic, DSP pipelines, and peripheral interfaces.
- Configuration: configured from an external PROM or via a serial/JTAG-based chain; reprogrammable as needed.
- Tool flow: supported by Xilinx ISE-based design flow and associated support software.
Typical use cases: lightweight embedded control, data-path buffering, custom interface controllers, and other mid-density logic tasks where cost and short development cycles matter.
In short: a mid-density, economical FPGA option in a 208-pin package for flexible, reconfigurable digital logic.
Key points:
- Density: about 200K system gates (roughly tens of thousands of logic elements).
- Package: 208-pin Plastic Quad Flat Gate (PQG208).
- Speed: -6 speed grade (faster timing options unavailable in this line).
- Architecture: configurable logic blocks (LUTs/FFs), distributed RAM, flexible I/O blocks across banks, suitable for glue logic, DSP pipelines, and peripheral interfaces.
- Configuration: configured from an external PROM or via a serial/JTAG-based chain; reprogrammable as needed.
- Tool flow: supported by Xilinx ISE-based design flow and associated support software.
Typical use cases: lightweight embedded control, data-path buffering, custom interface controllers, and other mid-density logic tasks where cost and short development cycles matter.
In short: a mid-density, economical FPGA option in a 208-pin package for flexible, reconfigurable digital logic.
Features
Here are the typical features of the XC2S200E-6PQG208C (Spartan-IIE FPGA):
- Family/device: Xilinx Spartan-IIE, XC2S200E
- Density: ~200K system gates
- Architecture: CLBs with 4-input LUTs and flip-flops; on-chip distributed RAM and shift registers
- I/O: 208-pin PQG208C package, usually supports about 100–120 user I/Os (in practice depends on I/O bank usage)
- Speed grade: -6 (moderate/fast for the family)
- Memory: distributed RAM resources; no modern BRAM blocks like in newer families
- Configuration: standard SPI/JTAG-based configuration options typical of Spartan-IIE devices
- Packaging: PQG208C (208-pin plastic quad flat package)
- Voltage/power: CMOS I/O compatible with typical Spartan-IIE designs; low-to-mid power for its era
- Applications: cost-sensitive mid-density logic, glue logic, simple DSP/pre-processing tasks
Note: exact I/O count and available RAM depend on bank/pin assignment in your specific design. For precise numbers, consult the official datasheet.
- Family/device: Xilinx Spartan-IIE, XC2S200E
- Density: ~200K system gates
- Architecture: CLBs with 4-input LUTs and flip-flops; on-chip distributed RAM and shift registers
- I/O: 208-pin PQG208C package, usually supports about 100–120 user I/Os (in practice depends on I/O bank usage)
- Speed grade: -6 (moderate/fast for the family)
- Memory: distributed RAM resources; no modern BRAM blocks like in newer families
- Configuration: standard SPI/JTAG-based configuration options typical of Spartan-IIE devices
- Packaging: PQG208C (208-pin plastic quad flat package)
- Voltage/power: CMOS I/O compatible with typical Spartan-IIE designs; low-to-mid power for its era
- Applications: cost-sensitive mid-density logic, glue logic, simple DSP/pre-processing tasks
Note: exact I/O count and available RAM depend on bank/pin assignment in your specific design. For precise numbers, consult the official datasheet.
Package
Plastic Quad Flat Pack with 208 pins (PQFP208); the “PQG208C” denotes a RoHS-compliant 208-pin PQFP package.
Pinout
- Pin count: 208 pins (PQG208C package)
- Function: Xilinx Spartan-2 FPGA (XC2S200E-6) – programmable logic device with ~200K system gates and I/O for digital designs.
- Function: Xilinx Spartan-2 FPGA (XC2S200E-6) – programmable logic device with ~200K system gates and I/O for digital designs.
Manufacturer
Manufacturer: Xilinx, Inc. It is an American multinational semiconductor company that designs and markets programmable logic devices (FPGAs, CPLDs, SoCs).
Application
Typical applications for XC2S200E-6PQG208C (Spartan-2E, ~200K gates):
- Embedded control and glue logic for consumer electronics
- DSP/signal processing accelerators in telecom and multimedia
- Video/image processing and display controllers
- Networking/communication equipment (protocol engines, interfaces)
- Data acquisition, instrumentation and test equipment
- Industrial automation and automotive sensor interfaces
- Rapid prototyping and ASIC/SoC verification
- Embedded control and glue logic for consumer electronics
- DSP/signal processing accelerators in telecom and multimedia
- Video/image processing and display controllers
- Networking/communication equipment (protocol engines, interfaces)
- Data acquisition, instrumentation and test equipment
- Industrial automation and automotive sensor interfaces
- Rapid prototyping and ASIC/SoC verification
出荷
出荷方法私たち
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出荷料参照(DHL/FedEx):
DHL の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は2〜5営業日です。
フェデックス: 配送費は25ドル〜40ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
UPS の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
TNT社: 配送費は25ドル〜65ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
EMS: 配送料金は30〜50ドル(0.5kg)の範囲で、推定配送時間は7〜15営業日です。
登録航空郵便: 配送費は2〜4ドル(0.1kg)で、推定配送時間は5〜20営業日です。
支払い
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