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SN74LVC126ABQAR
IC BUFF NON-INVERT 3.6V 14-WQFN
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- Mfr。パート #SN74LVC126ABQAR
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仕様
| Series | 74LVC |
| Part Status | Active |
| Logic Type | Buffer, Non-Inverting |
| Number of Elements | 4 |
| Number of Bits per Element | 1 |
| Output Type | 3-State |
| Current - Output High, Low | 24mA, 24mA |
| Voltage - Supply | 1.65V ~ 3.6V |
| Operating Temperature | -40°C ~ 125°C (TA) |
| Mounting Type | Surface Mount |
| Package | 14-WFQFN Exposed Pad |
| Supplier Device Package | 14-WQFN (3x2.5) |
| Packaging | Cut Tape (CT), Tape & Reel (TR) |
概要
Description
The SN74LVC126ABQAR is TI’s 4-bit buffer/line driver with 3-state outputs. It buffers four input signals to four outputs and can tri-state the outputs via enable controls, enabling bus sharing or level shifting between domains. Built on CMOS LVC technology, it operates from 1.65 V to 3.6 V, making it suitable for 3.3 V, 2.5 V, or 1.8 V systems. Applications include buffering data between a microcontroller/FPGA and peripherals, bus interfacing, and signal isolation.
The ABQAR suffix indicates Pb-free (RoHS) packaging, typically supplied in tape-and-reel; exact package type varies by catalog option. For precise drive strength, propagation delay, input thresholds, and the exact enable configuration, consult the TI datasheet and package drawings for this variant.
The ABQAR suffix indicates Pb-free (RoHS) packaging, typically supplied in tape-and-reel; exact package type varies by catalog option. For precise drive strength, propagation delay, input thresholds, and the exact enable configuration, consult the TI datasheet and package drawings for this variant.
Features
Here are the typical features of the SN74LVC126ABQAR:
- Quad buffer/line driver with 3-state outputs
- Noninverting data paths
- Two independent, active-low enable inputs (1OE and 2OE) that gate two output groups
- Outputs are high-impedance when disabled
- Single-supply CMOS (LVC) operates from about 1.65 V to 3.6 V
- CMOS input thresholds compatible with the supply
- Ioff support for partial-power-down (no back-powering when Vcc = 0)
- ESD protection on inputs/outputs
- Pb-free (RoHS-compliant) packaging (ABQAR)
- Quad buffer/line driver with 3-state outputs
- Noninverting data paths
- Two independent, active-low enable inputs (1OE and 2OE) that gate two output groups
- Outputs are high-impedance when disabled
- Single-supply CMOS (LVC) operates from about 1.65 V to 3.6 V
- CMOS input thresholds compatible with the supply
- Ioff support for partial-power-down (no back-powering when Vcc = 0)
- ESD protection on inputs/outputs
- Pb-free (RoHS-compliant) packaging (ABQAR)
Package
14-pin TSSOP (thin-shrink small-outline) package.
Pinout
- Pin count: 14 pins (D1–D4 inputs; Q1–Q4 outputs; G1–G4 enables; VCC and GND).
- Function: SN74LVC126ABQAR is a quad buffer/line driver with 3-state outputs. It provides four noninverting buffers, each with its own enable input; outputs go high-Z when disabled, suitable for bus buffering.
- Function: SN74LVC126ABQAR is a quad buffer/line driver with 3-state outputs. It provides four noninverting buffers, each with its own enable input; outputs go high-Z when disabled, suitable for bus buffering.
Manufacturer
- Manufacturer: Texas Instruments (TI).
- What kind of company: TI is an American multinational technology company that designs and manufactures semiconductors and integrated circuits, specializing in analog and mixed-signal ICs and embedded processors; one of the world’s largest semiconductor producers.
- What kind of company: TI is an American multinational technology company that designs and manufactures semiconductors and integrated circuits, specializing in analog and mixed-signal ICs and embedded processors; one of the world’s largest semiconductor producers.
Application
Typical applications of SN74LVC126ABQAR (quad buffer/line driver with 3-state outputs) include:
- Buffering address/data buses between microcontrollers/FPGA and memory/peripherals, with tri-state control.
- Level shifting and signal conditioning for mixed-voltage systems (e.g., 3.3V to others).
- Bus sharing and I/O expansion by gating outputs to prevent bus contention.
- Enhancing signal integrity on long interconnects with solid drive.
- General-purpose data buffering in backplanes and multi-device interfaces.
- Buffering address/data buses between microcontrollers/FPGA and memory/peripherals, with tri-state control.
- Level shifting and signal conditioning for mixed-voltage systems (e.g., 3.3V to others).
- Bus sharing and I/O expansion by gating outputs to prevent bus contention.
- Enhancing signal integrity on long interconnects with solid drive.
- General-purpose data buffering in backplanes and multi-device interfaces.
Equivalent
Equivalents (same function: 4-bit buffer/driver with tri-state outputs, same pinout/voltage range):
- 74LVC126A (Nexperia)
- MC74LVC126A (ON Semiconductor)
- 74AHC126 (various vendors; faster version)
Note: verify package, supply voltage (3.3V/5V), and OE/inputs polarity for exact compatibility.
- 74LVC126A (Nexperia)
- MC74LVC126A (ON Semiconductor)
- 74AHC126 (various vendors; faster version)
Note: verify package, supply voltage (3.3V/5V), and OE/inputs polarity for exact compatibility.
出荷
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出荷料参照(DHL/FedEx):
DHL の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は2〜5営業日です。
フェデックス: 配送費は25ドル〜40ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
UPS の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
TNT社: 配送費は25ドル〜65ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
EMS: 配送料金は30〜50ドル(0.5kg)の範囲で、推定配送時間は7〜15営業日です。
登録航空郵便: 配送費は2〜4ドル(0.1kg)で、推定配送時間は5〜20営業日です。
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