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MC74AC74DR2G
IC FF D-TYPE DUAL 1BIT 14SOIC
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- Mfr。パート #MC74AC74DR2G
- パッケージ
- データシート MC74AC74DR2G DataSheet
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仕様
| Supplier | onsemi |
| Package | Tape & Reel (TR),Cut Tape (CT) |
| Series | 74AC |
| ProductStatus | Active |
| Function | Set(Preset) and Reset |
| Type | D-Type |
| OutputType | Complementary |
| NumberofElements | 2 |
| NumberofBitsperElement | 1 |
| ClockFrequency | 160 MHz |
| MaxPropagationDelay@VMaxCL | 10ns @ 5V, 50pF |
| TriggerType | Positive Edge |
| Current-OutputHighLow | 24mA, 24mA |
| Voltage-Supply | 2V ~ 6V |
| Current-Quiescent(Iq) | 4 µA |
| InputCapacitance | 4.5 pF |
| OperatingTemperature | -40°C ~ 85°C (TA) |
| MountingType | Surface Mount |
| SupplierDevicePackage | 14-SOIC |
概要
Description
MC74AC74DR2G is a dual, D-type, positive-edge-triggered flip-flop with asynchronous preset and clear. Each of the two flip-flops (A and B) has: D input, clock (CLK), Q and Q̅ outputs, and asynchronous PRE (set) and CLR (reset) inputs. Operation: when PRE is low, Q goes high; when CLR is low, Q goes low; when PRE and CLR are both high, on a rising edge of CLK the Q output follows D. Q̅ is the complement of Q. This device is from the 74AC family (high-speed CMOS), typically operating from a supply in the 2.0–5.5 V range with low static power and CMOS-compatible inputs. Package DR2G denotes a specific surface-mount package variant (14-pin). Common uses include data storage/registers, shift registers, timing and synchronization circuits, and state machines. For exact pinout, timing, and electrical specs, refer to the datasheet.
Features
MC74AC74DR2G features:
- Dual D-type flip-flops, positive-edge triggered
- Independent asynchronous inputs: preset (P) and clear (CLR) active-low
- Q and Q̄ outputs for each flip-flop
- Wide supply voltage range (CMOS): typically 2.0 V to 6.0 V
- Low-power CMOS technology with high noise margin
- High-speed operation with standard CMOS I/O
- DR2G package option (compact dual-flip-flop device) suitable for synchronous logic designs
- Dual D-type flip-flops, positive-edge triggered
- Independent asynchronous inputs: preset (P) and clear (CLR) active-low
- Q and Q̄ outputs for each flip-flop
- Wide supply voltage range (CMOS): typically 2.0 V to 6.0 V
- Low-power CMOS technology with high noise margin
- High-speed operation with standard CMOS I/O
- DR2G package option (compact dual-flip-flop device) suitable for synchronous logic designs
Package
14-pin SOIC (D‑package), RoHS compliant (G), with tape‑and‑reel packaging (R2).
Pinout
Pin count: 14 pins (DIP-14/SOIC-14; package code DR2G).
Function: Dual D-type, positive-edge-triggered flip-flop with asynchronous active-low preset (PRE) and clear (CLR). Each flip-flop has D, CP (clock), PRE, CLR inputs and Q, Q̄ outputs. On rising edge of CP, Q follows D; PRE asynchronously sets Q to 1; CLR asynchronously clears Q to 0; Q̄ is the complement. Two independent flip-flops in one package.
Function: Dual D-type, positive-edge-triggered flip-flop with asynchronous active-low preset (PRE) and clear (CLR). Each flip-flop has D, CP (clock), PRE, CLR inputs and Q, Q̄ outputs. On rising edge of CP, Q follows D; PRE asynchronously sets Q to 1; CLR asynchronously clears Q to 0; Q̄ is the complement. Two independent flip-flops in one package.
Manufacturer
Manufacturer: ON Semiconductor.
What kind of company: A global American semiconductor company that designs, manufactures, and markets integrated circuits and other silicon devices for automotive, industrial, communications, computing, and consumer markets.
What kind of company: A global American semiconductor company that designs, manufactures, and markets integrated circuits and other silicon devices for automotive, industrial, communications, computing, and consumer markets.
Application
MC74AC74DR2G is a dual D-type positive-edge-triggered flip-flop with asynchronous clear (CLR) and preset (PRE). Common applications: data storage and registers in digital systems; edge-triggered storage for pipelines; shift registers and sequence generation; simple counters and state machines; clocked data synchronization and timing control; initialization of flip-flops using PRE/CLR.
Equivalent
Equivalent parts (same function: dual D flip-flop with async clear/preset):
- TI SN74AC74 (and SN74AC74DR/DR2G in similar packaging)
- NXP/ON Semiconductor 74AC74
- 74HC74 (CMOS)
- SN74ACT74
- 74HCT74 (TTL-compatible)
Note: verify Vcc range, input thresholds, and exact pinout before substitution.
- TI SN74AC74 (and SN74AC74DR/DR2G in similar packaging)
- NXP/ON Semiconductor 74AC74
- 74HC74 (CMOS)
- SN74ACT74
- 74HCT74 (TTL-compatible)
Note: verify Vcc range, input thresholds, and exact pinout before substitution.
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出荷料参照(DHL/FedEx):
DHL の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は2〜5営業日です。
フェデックス: 配送費は25ドル〜40ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
UPS の: 配送費は25ドル〜45ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
TNT社: 配送費は25ドル〜65ドル(0.5kg)の範囲で、推定配送時間は3〜7営業日。
EMS: 配送料金は30〜50ドル(0.5kg)の範囲で、推定配送時間は7〜15営業日です。
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